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merge #8

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git-svn-id: http://svn2.nishi.boats/svn/milsko/trunk@545 b9cfdab3-6d41-4d17-bbe4-086880011989
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IoIxD
2025-11-01 04:32:06 +00:00
parent d1697ed46a
commit 0b5463e1d1
3 changed files with 69 additions and 12 deletions
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36
src/math/math_internal.h
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@@ -3,8 +3,44 @@
#ifndef __MW_LOWLEVEL_INTERNAL_MATH_H__
#define __MW_LOWLEVEL_INTERNAL_MATH_H__
#include <Mw/BaseTypes.h>
#include <Mw/LowLevelMath.h>
/* Bitfield of cpu features we get from x86's CPUID */
#if defined(__WATCOMC__) || defined(__i386__) || defined(__amd64__)
typedef struct _cpuFeatures cpuFeatures;
struct _cpuFeatures {
MwBool fpu : 1; /* x87 FPU on chip */
MwBool vme : 1; /* Virtual-8086 Mode Enhancement */
MwBool de : 1; /* Debugging Extensions */
MwBool pse : 1; /* Page Size Extensions */
MwBool tsc : 1; /* Time Stamp Counter */
MwBool msr : 1; /* RDMSR and WRMSR Support */
MwBool pae : 1; /* Physical Address Extensions */
MwBool mce : 1; /* Machine Check Exception */
MwBool cx8 : 1; /* CMPXCHG8B instr */
MwBool apic : 1; /* APIC on Chip */
MwBool sep : 1; /* SYSENTER and SYSEXIT instrs */
MwBool mtrr : 1; /* Memory Type Range Registers */
MwBool pge : 1; /* Page Global Bit */
MwBool mca : 1; /* Machine Check Architecture */
MwBool cmov : 1; /* Conditional Move Instrs */
MwBool pat : 1; /* Page Attribute Table */
MwBool pse36 : 1; /* 36-Bit Page Size Extension */
MwBool psn : 1; /* Processor Serial Number */
MwBool clflush : 1; /* CLFLUSH instr */
MwBool ds : 1; /* Debug Store */
MwBool acpi : 1; /* Thermal Monitor and Software Controlled Clock Facilities */
MwBool mmx : 1; /* Intel MMX Technology */
MwBool fxsr : 1; /* XSAVE and FXRSTOR Instrs */
MwBool sse : 1; /* SSE */
MwBool sse2 : 1; /* SSE2 */
MwBool ss : 1; /* Self Snoop */
MwBool hit : 1; /* Max APIC IDs */
MwBool tm : 1; /* Thermal Monitor */
MwBool pbe : 1; /* Pending Break Enable */
};
#endif
#include "nbsd_math.h"
struct _MwLLMathVTable {